FIGS. 1A and 1B are circuit diagrams of an example of a conventional non-volatile semiconductor memory, specifically showing a main part of a memory cell portion of an EPROM. Referring to FIG. 1A, 1 represents an EPROM cell constituting a memory cell; 2 a word line; 3 an enhancement nMOS serving as a load transistor; 4 a power line for supplying a power supply voltage Vcc of, for example, +5 [V]; 5 an amplifier; and 6 an output terminal.
FIG. 1B is a circuit diagram showing a configuration of an amplifier 5. The amplifier 5 of FIG. 1B is an inverter constructed by a cascade connection of inverters 51 and 52. There is a feedback from a point midway between the inverters back to a PMOS transistor 53, resulting in a high-speed build-up of the circuit.
In such a memory cell portion, if a power supply voltage Vcc is set for the word line 2 when no electrons are injected into a charge storage gate of the EPROM cell 1, i.e. a so-called floating gate (when nothing is written thereto; in other words when a logic state of the memory is "1"), then the EPROM cell 1 is turned ON and a current flows from the drain to the source of the EPROM cell 1. As a result, the level of voltage of a node 7 drops to 0 [V], which voltage is output to the output terminal 6 via the amplifier 5.
On the other hand, if a power supply voltage Vcc is set for the word line 2 when electrons are injected into the floating gate of the EPROM cell 1 (when something is written thereto; in other words when a logic state of the memory is "0"), the EPROM cell 1 is not turned ON and a current does not flow from the drain to the source of the EPROM cell 1. As a result, the level of voltage of the node 7 rises to the power supply voltage Vcc [V], which voltage is output to the output terminal 6 via the amplifier 5.
In other words, in such a memory cell portion, the nMOS 3 which serves as a load transistor is designed in such a manner that the voltage of the node 7 is 0 [V] when nothing is written in the EPROM cell 1, i.e., when the logic state thereof is "1", and the voltage of the node 7 is Vcc [V] when something is written in the EPROM cell 1, i.e. when the logic state thereof is "0".
However, such an EPROM has a disadvantage in that, despite the writing of the logic "0" into the EPROM cell 1, i.e. despite the injection of electrons into the floating gate of the EPROM cell 1, the electrons in the floating gate of the EPROM cell 1 are depleted by being heated in a subsequent assembly process or an acceleration test.
The effect of such a depletion of electrons increases greatly as the size of the EPROM cell 1 is reduced, presenting a serious problem with regard to the large-capacity memories currently used. It should also be noted that such a depletion of electrons occurs as a result of age deterioration.
The above disadvantage leads to a problem in that, in case a plurality of the semiconductor memories described above are used in a redundancy address memory circuit (see FIG. 6), the function of switching to a redundancy cell, which switching becomes necessary when a defect occurs anywhere in a cell array, can not be fully accomplished because of the depletion of electrons from the floating gate during the above-mentioned assembly process, for example.